In the realm of computer systems, memory serves as a crucial component that acts as a storage repository
for both data and instructions.
As we have previously previously explored, there exists specialized storage elements called registers
that enable high speed access to critical information.
So while registers provide rapid data retrieval, it's important to acknowledge that memory access operates
at a comparably slower pace.
So this discrepancy in access speed necessitates a careful balance between the usage of registers and
memory to optimize overall system performance.
So registers represent the pinnacle of the memory hierarchy due to the their immediate accessibility
by the processor.
So they facilitate rapid execution of instructions by providing quick access to frequently used data.
However, the abundance of registers is inherently limited due to the physical and design considerations.
This limitation prompts the integration of various memory levels, each with distinct access speeds,
capacities and costs.
So diving deeper, we we encounter the theoretical limit of memory size, which boasts around 264 addresses.
Let's actually open the grommet.
And as always, throw things on the screen.
So.
Uh, 264 addresses.
So to put this into perspective, this limit translates at staggering, like 16 exabytes.
Exabytes.
Which is a lot.
It's 6000 exabytes of memory.
While this figure appears remarkably large, it is vital to note that practical implementation constraints
prevent the utilization of such a colossal memory capacity.
And while the theoretical memory capacity seems virtually boundless or the real world, design considerations
inevitably impose limitations on its effective utilization.
So various factors contribute to these constraints.
Physical space requirements, manufacturing capabilities, power consumption and cost considerations
collectively influence the decision making process when determining memory sizes for a given system.
Thus, the pursuit of an ideal balance between memory capacity and practicality becomes an intricate
endeavor.
So now what we're going to do is we will open the our.
Chrome and see.
What a 16 exabytes equals here.
16.
Bites here.
Let's actually turn the exabytes to gigabytes and 116 exabytes to gigabytes.
And as you can see here, this is something like this gigabytes here.
And realizing the memory subsystem that harnesses the full potential of the theoretical memory limit
is a formidable challenge.
So as the memory capacities increase, new architectural innovations must emerge to address the associated
complexities.
So these challenges encompass efficient memory, addressing data integrity, error correction mechanisms
and ensuring uniform access speeds across the memory hierarchy.
Overcoming these obstacles is vital to harnessing memories to potential.
So in conclusion, memory emerged as a cornerstone of modern computing systems functioning as a repository
for data and instructions vital to processor operations.
And while registers offer expedited access, the memory hierarchy accommodates the need for scalable
storage solutions.
Memory access governed by the addressing mechanisms navigates through different memory types, each
tailored to specific access requirements.
So the theoretical memory limit presents an A1 sparring figure of 604 sorry for this 264 addresses showcasing
the man's potential for memory capacity.
However, practical design factors such as physical limitations, manufacturing capabilities and economic
considerations steer memory capacities towards more manageable levels.
As we push the boundaries of computing, the pursuit of optimal memory architecture becomes a dynamic
process requiring innovative solutions to address challenges associated with expanding memory capacities.
By understanding the intricate interplay of memory, technical intricacies and practical constraints,
we pave the way for enhanced computing experiences that leverage the true power of memory.
Now we will develop an application again here 64 bit and an Nasm application here.
Let's create a new project.
Delete this this We will name this project as.
Uh, memory or actually, let's make me name it our the 16 exabyte.
Let's actually name it Exabyte here x a byte so we can remember it takes a byte more how much it how
big is it?
So we will create a section data section data here.
So we will define numbers.
We will define byte size variable, be num with the value.
One, two, three.
We num db one, two, three and we will define a word size variable w num with value.
One, two, three, four five.
We num w one, two, three, two, one, two, three, four, five.
And we will define an array of five words and initialized to zero w array.
Times and 5W0.
And dinam.
ID one, two, three, four, five.
Here we define the.
Let's actually make it an uppercase.
So the D this is a double word size variable name with value.
One, two, three, four, five.
We will define the num one to num one.
The Q here as well.
One, two, three, four, five.
We are here.
We are defining the quadword size variable q num one with value.
One, two, three, four, five and text one db.
A, B.
C here.
Zero.
Here we are defining a null terminated string variable text one with value.
A, b, c.
And the num to.
The queue here.
Here we will define a quadword size variable name with the value of P.
It's actually 3.14 and 1592.
60 for.
Uh, no.
Yeah.
Uh, 92, 65 four.
And after that, we will define a null terminated string variable text to with the value.
See the E here.
At the null termination as well.
And that's it.
We will go to section B here.
Section.
Action.
And now what we're going to do is we will define four variables.
We will reserve four variables here.
We defined already.
We are defining variables in data section.
So now we will reserve one byte of space for variable.
Be var in this section, be var rest be.
Recipe.
And one.
And we will also define not defined.
We will reserve the four bytes of space.
We will reserve four bytes of space variable for base for variable D, var in the base section.
And W.
We will reserve space for an array of.
Uh, ten words.
Named W4 in the S section.
As well.
We will define a reserve keyword.
A rest.
Q three.
Here we are reserving space for an array of three quad words named Q R in the spaces section as well.
And this is the last reserve that we defined in this section.
Now we will continue to the section text.
And here we will define the.
Global.
Maine.
Global.
Maine.
Main.
And in this main here.
RPM.
We are pushing the value of P onto the stack.
We will move the value of RSP into P, which is also setting up the stack frame.
P.
RWP rsp and we will load the memory of address this binom into rax.
Leah.
Racks.
To be numb.
And we will move the racks.
So we will load the value stored at Benham.
Interacts.
But here we load the memory address of p'num interacts and now we are loading the value stored at p'num
into Rax here.
Venom.
And here we will again load the value stored at memory, address stored and Bynum interacts.
I will explain this further.
This is new to us.
So move.
Bois.
PVR.
Racks.
No, actually, yeah, we.
We need to move the.
Move the racks to.
Leah move.
And now.
Yes, this is true.
So what we did here, we.
We loaded the value stored at memory address, which is stored in Benham into racks here again.
Now, what we're going to do is we will move the PVR.
We were.
As you can see, we are using this section which we reserved in previous year in this section.
Section.
Now we will store the value in rax at the memory address of Bois.
Rags and.
We completed three move instruction here.
Now we will use the Lia here to rax.
We are loading the memory address of bvar into rax here.
Racks.
PVR.
But remember, here we store the value in racks at the memory address before.
Actually, if we write this command, if I write the comments here to this code, you will understand
it better.
Posh, the less actually it will be quicker.
Don't worry posh the value of RVP onto the stack and.
And here we are.
Uh, let's see.
We are moving the move.
Move the value of RSP.
Let's make it uppercase, RVP.
So move the value of RSP into RVP, which is.
This is the setting up the stack frame.
And here.
We are not.
The memory address of numb into.
Racks.
And here we are telling the assembly to load the load, the value stored.
Add venom into racks.
Here we are telling the assembler to load.
The value stored.
At.
Saw that on here and.
Yeah.
Load the value stored at the memory address.
Memory address stored in penam into rax.
And after that we we are telling the assembly to store the value in racks.
Racks at the memory Address of Beaver.
And after that we are telling.
The assembly to load the load the memory address.
Load the memory address of PVR, PVR into Rax.
And now we will continue our code writing here.
So we will use another instruction.
Now we are.
Junior here the racks to double numb.
This is for load the memory load the memory address of w num into rax.
Again, we will know not.
Yes, we will load the value stored at w num into rax.
Racks.
W nam.
The load.
The value.
Or load the so here rax w num we wrote here.
So we loaded the memory address of the num into rax.
But now what we're going to do is we are going to load the value.
Go to the value part.
In w num into rax and here we will use the Lia again because we need to tell the Assembly to load the
memory address of text one.
In two racks.
Right.
So racks.
Text one.
I will also add the comments load the memory memory address of text one into Rax and now we will tell
the assembly to load the memory address of text one into.
Racks.
Thanks one.
Load the memory address.
Of text one.
Interacts.
And here you might be asking why the comments here is same.
So you will learn that in when we get the output from this program.
So don't worry about it.
And after that we will need to load the value as the second character of Text one into Rax.
In this case, the second character is here.
So.
Move there.
Move.
Now we will use the Mu again.
Two racks.
Text one plus one.
Here we are telling the.
The memory address of text.
Now load the value at the second character of text.
One one interacts.
And we will use again.
La Rocks here.
And now, as we always do now, we will need to load the memory address of the second character of Text
one into Rax.
In order to do that, we will use this braces here.
So text one plus one.
What's the price?
Now we are telling the Lord the.
Load the memory.
Memory address.
Of text one.
Memory address of text one plus one into Rax.
Now we need to just write.
Actually not here.
So he wrote.
MOV rax text one.
So we've done this right and we use the Leah here.
Although the memory address of the second character memory address of now loads the memory address of.
The of the second character of text one interacts.
And now we just need to write five more instructions.
And we are done with this code here and in, in next lecture, we will analyze it, debug it and so
on because the you will learn a lot from this code here about, uh, manipulating and using memories
in assembly language.
So after here we will need to use, uh, move here.
So move rax.
Next one.
Here we are telling the assembler to load.
The value stored.
At the memory address of text one.
Text one interacts.
And after that we will use the move again to racks to load the value stored at the memory address of
text one plus one into rax.
So.
Uh, text.
X one plus one.
You're telling the Lord the value.
Thought.
At the memory Memory address.
Of text one plus.
Text one plus one interacts.
And now we just we will need to restore create the exit codes here.
So RSP rbp.
This is for restore.
Restore.
The value of RSP from which we need to do this for cleaning clean.
Clean up the stack frame.
And after that we will.
Pop.
Value of from the stack.
Up the value of rb P from the stack.
Write it up.
The value of P from the stack.
And now we will return from the function.
Return from the function.
So that's it.
You need to develop this following program which exhibits a lack of discriminable output here.
But we will employ a debugger to meticulously traverse each program instruction.
This is a favorable option in the context of this employment of CSM.
So I will explain this code in next lecture and meeting you in the next lecture.